10/16/2018

Part 2: Metrology for TSV Fabrication

Series: Advanced Packaging - Multi-Sensor Metrology for Every Process Step

Three-dimensional integrated circuit (3D IC) and 2.5D IC with Si interposer are regarded as promising candidates to overcome the limitations of Moore’s law because of their advantages of lower power consumption, smaller form factor, higher performance and higher function density. To achieve 3D and 2.5D IC integrations, several key technologies are required. Through-silicon via (TSV) is a key technology to perform system-level integration with smaller package size, higher interconnection density and better performance. Since TSV provides the advantages of shortened interconnection paths and thinner package size, it is considered as the heart of 3D integration to permit communications between various sections of the 3D integration system.

A TSV is a direct vertical connection between different levels of a chip. It consists of a conducting via which passes through the silicon substrate and connects the two sides of the wafer. Typically, the interplane via is etched and filled with metal, such as tungsten or copper. The features of a TSV are dependent of its electrical parameters, such as metal conductivity, dielectric permittivity and geometrical characteristics. In particular, the pitch and the aspect ratio of the TSV have a strong impact on the distribution of the TSVs during the fabrication process. TSV pitch is defined as the distance between two TSVs, while the TSV aspect ratio is determined as the ratio between the depth and the diameter of the TSV cavity. Usually, TSV structures are manufactured as an array in a silicon substrate. Large size TSVs have diameters larger than 10 μm, small aspect ratios of about 1 or 2, and serve as bond-pad interconnects in 3D-WLP technologies. In 3D-SICs, medium size TSVs are used as global interconnects with diameters between 2 μm and 10 μm, while the smallest size TSVs are used at the local interconnect level.

3D integration technologies with TSVs can be realized by employing several methods, which usually involve a sequence of wafer thinning and handling, TSV formation, stacking orientation and bonding. The sequence of these basic technology modules may vary, resulting in different fabrication process flows. Diverse process approaches can be developed by changing the order of the TSV fabrication with respect to the device wafer fabrication to obtain the so-called "via first", "via middle" or "via last" process sequences. The choice of TSV schemes is based on the final application requirement in the industry. TSV technology has been developed for many applications, such as MEMS, mobile phone, CMOS image sensor (CIS), bioapplication devices and memory products.

 

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Part 1/3: Metrology for Semiconductor Lithography

Part 3/3: Metrology for RDL, UBM and Solder Bump Fabrication

 

Furthermore, TSV fabrication has various important processes, including via formation by deep reactive ion etching (DRIE), lining with dielectric layer, barrier and seed layers, via filling and chemical mechanical polishing (CMP).

TSV etching is a key fabrication module in 3D integration technologies. However, it inevitably causes sidewall scalloping roughness which may induce poor step coverage of following processes, resulting in electrical leakage and reliability issues. Developing the right amount of sidewall roughness in etching is a matter of balancing the etching and passivation process. The sidewall scalloping impacts dielectric, barrier and Cu seed layer coverage by enhancing the voids in the TSV. Thus, the sidewall scalloping needs to be minimized as the size of TSV reduces.

The conducting material is electrically isolated from the silicon wafer by a dielectric layer, typically made of silicon dioxide (SiO2) and called TSV liner. The function of the insulator is to prevent leakage and resistive coupling through the silicon. Process requirements for a dielectric layer include good step coverage and uniformity, no leakage current, low stress, higher breakdown voltage and processing temperature limitations due to different TSV integration.

Furthermore, a barrier layer between the dielectric layer and the conductor avoids the metal diffusion into the silicon substrate during annealing processes that require temperatures around 400 °C. The common materials that are used as barrier layers are Ti, Ta, TiN and TaN.

After barrier layer deposition the TSVs can be filled with metal using three different plating methods: conformal plating, sealing bump with bottom-up plating and super-conformal plating. The plating methods are based on various 3D integration applications. The TSV depth is defined by the required thickness during chip or wafer stacking and the aspect ratio is determined by the production of the dielectric layer, the barrier layer and the filling process.

Finally, CMP is used to remove the Cu overburden as well as barrier layer from the wafer surface and planarize the TSVs. In general, this technology requires two steps. The first step is to remove the thick copper cap with dimples or recesses after TSV filling, which stops at the barrier layer. The second step removes the barrier layer, stopping at the dielectric layer. Different suspensions with selectivity are used to realize good insulation, a smooth surface and avoid defects like dishing and erosion.

The flexible and modular multi-sensor measuring tools of the MicroProf® series offer optical and non-contact innovative solutions in the field of TSV fabrication for production and R&D. Where other systems reach their limits, the measuring tools of the MicroProf® series fulfill the permanently increasing demands on production parameters, process control and quality assurance.

For example, deep trenches have depths from 50 to 200 μm far beyond the reach of AFM or profilometer tips. Additionally, the etching process results in a roughening of the surface in the etch trenches and thus in high differences in reflectivity between the substrate surface and the bottom of the trenches, which can lead to measurement problems. Thanks to its parallel illumination, the WLI PL is ideally suited for measuring such deep trenches with a high aspect ratio, since a large proportion of the light reaches the bottom of the etching structure and the depth can thus be measured. Depending on the surface condition, structures with minimum widths of 2 to 3 μm and aspect ratios of up to 50:1 (depth to width) can be measured.

Another problem for the measurement technology is often the small lateral dimension of the structures, since the optical resolution of the techniques is usually not sufficient to resolve them. With the help of a special algorithm, the WLI FL makes it possible to determine the depth of etching structures with widths down to 0.7 μm, which is already below the optical resolution limit of this measuring method. In this case the aspect ratio can be up to 3:1. This opens up dimensions that have not yet been reached before. With this method, all currently used variants of TSVs can be measured, including those vias with diameters below one micrometer that can actually not be optically detected. It is important to note that the individual via is measured and not a statistical effect.

With our 3D surface measuring tools of the established MicroProf® series, area measurements as well as single and multiple profiles can be acquired without contact. There is the possibility of automated mapping of the samples, as well as the execution of evaluation routines. Roughness, even on transparent layers, can be determined down to the sub-nanometer range, and topography measurements of TSVs can be performed.

A further domain of our measuring tools is the layer thickness determination of coatings, e.g. insulating and protective layers, in the form of thin films or layer stacks. Layer thicknesses of up to several nanometers can be determined, with a resolution in the sub-nanometer range.

Another application is the measurement of defects after the individual TSV process steps. Defects are for example photoresist residues, cracks, delaminations and voids of the deposited layers, recesses and copper protrusions after filling, as well as dishings and erosions after CMP. In the CMP process, it is also necessary to ensure that the thickness is observed over the entire wafer in the range of a few micrometers, roughness parameters are achieved and that the flatness over the entire CMP area is uniform.

All tools of the MicroProf® series offer a complete analysis of topography and TTV. A fully automated EFEM (equipment front end module) also supports the processing of thin wafers. Due to the multi-sensor concept, the tools can be retrofitted with different sensors, e.g. IR sensors for layer thickness determination, at any time. A combination of different measuring tasks in one tool is therefore possible.

With the MicroProf® series a 100% inspection after each process step in TSV fabrication is possible.

Whether for laboratory, development, quality assurance or production - FRT offers the right measurement technology for your application from Advanced Packaging. Do not hesitate to contact us if you have any questions. Our experts will be glad to support you in solving your measurement tasks by creating the best possible system configuration for you.

Interested in latest posts of this series? Click below.

Part 1/3: Metrology for Semiconductor Lithography

Part 3/3: Metrology for RDL, UBM and Solder Bump Fabrication