11/20/2018

Part 6: Metrology for 3D Chip Stacking

Series: Advanced Packaging - Multi-Sensor Metrology for Every Process Step

3D chip stacking is the process of placing several dies on top of each other in a single semiconductor component. Chip stacking increases the silicon chip area that can be placed in a component with a given size. It also saves valuable board space and simplifies the assembly process. In addition to saving space, chip stacking also improves the electrical performance of the components because the shorter path of the connections between circuits results in faster signal transmission and reduced noise.

The first applications of stacked dies were stacking two memory chips on top of each other, such as Flash and SRAM components. Meanwhile, die stacking technology has extended from memory chip stacking to six or more chips with different functions or technologies. Die stacking has become synonymous for the integration of vertical circuits instead of the traditional planar design.

The connection of the stacked dies in one component is a particularly challenging task, especially when wire bonding is used. Mechanical fineness plays a decisive role in the complex design of hundreds of microscopic wires. The stacked dies can be connected by wire bonding alone or by a combination of wire bonding and flip chip bonding. The use of wire bonding as the only bonding method is limited because each die must be wired individually to the substrate. This limits the number of stacked dies that can be connected to a maximum of three. A die that is wired to the substrate must have a 0.5-1 mm exposed surface surrounding its outer area to enable the formation of the necessary loops during wiring. Die-to-Die wire bonding is also performed, but the lower die must be sufficiently larger than the upper die to provide sufficient space for the wire bonding connections. Wire bonding of stacked dies requires loop heights of less than 100 microns. This is a much greater challenge than the loop heights of 150 to 175 microns occurring with conventional wire bonding of unstacked dies. At a time when digital, analog and RF circuits need to be integrated, the use of two connection technologies (wire bonding and flip chip bonding) is essential to achieve the desired results. One of the important steps is to develop and assembly fine pitch and high density solder microbumps. Solder microbumps for flip chip interconnections allow high wiring density in the Si-carrier and enable high-performance signal and power connections.

 

Interested in latest posts of this series? Click below.

Part 1/8: Metrology for Semiconductor Lithography

Part 2/8: Metrology for TSV Fabrication

Part 3/8: Metrology for RDL, UBM and Solder Bump Fabrication        

Part 4/8: Metrology for Carrier Bonding/ Debonding, Backside Thinning and Nail Reveal

Part 5/8: Metrology for Wafer Dicing

Part 7/8: Metrology for Molding of 3D Chip Stacks

Part8/8: Metrology for Every Process Step in Advanced Packaging

 

Stacking dies is associated with many other requirements. One of these is the need to fix the die stack thermally and mechanically stable on the substrate. At the same time, the resulting component must be as thin as possible, with electrically perfect and reliable connections. Of course, the final thickness of the component depends on the number of dies in the stack.

Wafer thinning, thin-wafer-handling and thin-die-attach are essential elements for successful chip stacking. Wafer-thinning involves conventional wafer back-grinding, followed by a polishing step that reduces the stresses transferred to the wafer by the back-grinding process. Particularly thin wafers are very fragile and require special gripping and handling systems to ensure the required stability at all times. In particular, stacking very thin dies can be a major challenge.

Another requirement in chip stacking is the ability to select the good dies from a wafer and identify the bad dies. The incidental use of defective dies in the chip stack leads to yield losses and higher costs.

Substrate thickness is also an important factor in die stacking. The thickness of the substrate contributes to the overall thickness of the component. This means that at a given component height, increasing the substrate thickness reduces the number of dies that can be stacked on it. The core thickness and the number of laminate layers finally define the total substrate thickness.

3D chip stacking thus becomes more difficult and more expensive with increasing number and complexity of the dies to be stacked. 

FRT's multi-sensor measuring tools combine various measuring methods and sensors to measure a wide range of surface properties such as geometry, 3D topography and flatness of dies, as well as finished semiconductor components with high precision.

The automation includes two aspects: the automation of the measuring process itself and the integration into the automated production processes. The first enables as many operators as possible to control product quality after the stacking process. One-button solutions have become established for this purpose: Automatic measuring programs for different processes, parameters and ranges, which the operator can run at the touch of a button after placing the sample on the machine. With such solutions, even complex measurements on dies are abstracted to understandable "good/bad evaluations", for example.

The second aspect in the automation of the measuring process is the sample placement. In the field of wafer technology, different handling and grabber systems can be used to simplify and speed up the loading process. Powerful image acquisition hardware, intelligent pattern recognition, integrated calibration and automated measuring processes ensure short throughput times and reproducible results with the MicroProf®. It is also crucial to integrate the results into the production processes. A good software platform for the measuring tools then transfers the information obtained directly to the next step in the production line via a SEMI-compliant SECS/GEM interface.

The industry is increasingly trying to integrate optical 3D measurement technology directly into the production line (the so-called inline area) and thus enable 100% control of various parameters. This is done for good reason: Automated optical surface measurement ensures that measurement processes are reliable, fast, reproducible and verifiable. This means a development boost for quality assurance in production.

In order to always tailor our tools to the current customer demands, we have expanded our product portfolio and offer our surface measuring tools optionally with a thermo unit. Our thermo unit with fully integrated heating and cooling stage enables high-precision temperature control of die stacks and fully assembled semiconductor components. The temperature range extends from 10°C or -80°C (liquid nitrogen cooling) up to 400°C with a fast heating and cooling rate and a homogeneous temperature distribution on the sample surface. The temperature is set via a closed control circuit. Measurements can thus be carried out at a constant temperature as well as while driving a temperature ramp.

The thermo unit is available in various sizes and is easily mounted on the MicroProf® sample table. The thermo unit can be cooled with CDA or liquid nitrogen and even purged with different mediums to create defined ambient conditions.

In the field of electronic components, temperature-induced deformations of individual materials on a printed circuit board can lead to fractures. Individual components can be better matched to each other by evaluating the temperature-dependent behavior of the used materials. This increases the thermal durability of the resulting component. The topography can now also be measured as a function of temperature. Deformations of a sample due to thermal influences, as well as shape stability under defined ambient temperatures can now be determined with the help of FRT products.

The thermo unit is available as an extension for all FRT tools and is mounted as a separate module like a normal sample holder.

In addition to temperature-dependent topography measurements, the MicroProf® can be extended with the microDAC® TL, which includes a 2D deformation sensor from CWM. In addition to measurements outside the plane (warpage), the microDAC® TL enables the investigation of deformations in the plane from individual electrical components to complete assemblies. With the high-precision camera setup global and local deformation fields can be measured with an accuracy of up to 50 nm. The field of application is the detection of weak points of electronic assemblies under internal or external loads, such as temperature-related deformations or deformations due to assembly. The system is particularly advantageous in combination with numerical simulation. As an input for the simulation, thermo-mechanical material data can be determined as well as simulation results can be verified on the basis of the deformations.

In combination with the FRT software Acquire Automation XT the thermo unit can execute fully automatic temperature profiles. The user can set target temperatures, temperature ramps and dwell times to be used during the process. It is also possible to define set points at which topography and deformation measurements are performed in the heating/cooling process. Permanent temperature logging is available, optionally a second temperature probe can be added to control the temperature at specific locations on the sample.

In this way, the MicroProf® can be used to characterize the lateral and vertical deformation of samples under thermal load. The behavior of components under working conditions can be determined and various process steps can be simulated.

Whether laboratory, development, quality assurance or production - FRT offers the suitable measurement technology for your application from Advanced Packaging. Do not hesitate to contact us if you have any questions. Our experts will be glad to help you solve your measurement tasks by creating the best possible system configuration for you.

Interested in latest posts of this series? Click below.

Part 1/8: Metrology for Semiconductor Lithography

Part 2/8: Metrology for TSV Fabrication

Part 3/8: Metrology for RDL, UBM and Solder Bump Fabrication        

Part 4/8: Metrology for Carrier Bonding/ Debonding, Backside Thinning and Nail Reveal

Part 5/8: Metrology for Wafer Dicing

Part 7/8: Metrology for Molding of 3D Chip Stacks

Part8/8: Metrology for Every Process Step in Advanced Packaging