Series: Advanced Packaging - Multi-Sensor Metrology for Every Process Step
Over the years, the semiconductor industry has increasingly focused on reducing gate dimensions to improve performance. This focus has now moved to packaging as customers move from wire bonding to flip-chip wafer level packaging (WLP), while fan-out wafer level packaging (FOWLP) and 3D IC packaging become increasingly important. The typical connection mechanism between different dies or 3D stacks is realized by solder bumps in flip-chip technology, which is in contrast to the older wire bonding technology. In particular, a higher number of dies can be integrated by using an array of solder bumps to connect silicon chips to the substrates.
Flip-Chip is a 3D WLP bonding technology that connects the levels of the 3D stack with solder bumps. After the ICs are generated on the wafer, the chip pads are metallized on top of the ICs in the final wafer processing step and solder bumps are applied to each of the chip pads. To attach the wafer to another substrate, it is aligned with the solder balls facing the bond pads on the substrate.
During the solder bump fabrication process, a thin-film under bump metallization (UBM), usually made of nickel (Ni), is applied to the chip bond pads to separate the solder bump from the surrounding metallic interconnect lines on the chip side. The selection of a suitable UBM layer becomes a key process for the development of reliable flip-chip solder bumps. The main function of the UBM layer is to reduce the maximum temperature near the contact between the solder bump and the surrounding metal line in order to increase lifetime. On the substrate side, the metallic bond pad allows contact between the solder bump and the metallization on the substrate.
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Solder bumps are important features of the 3D stacking process because they perform several functions in the flip-chip array. The solder bumps provide both the electrically and thermally conductive paths to transfer electrical current and heat from the chip to the substrate. They also provide mechanical support for mounting the die on the substrate by reducing the mechanical stress between the chip and substrate.
The typical diameter of a flip-chip solder bump for 3D WLP technology ranges from 100 μm to 200 μm. Improvements in bond processing technology have led to a reduction in the diameter of the solder bumps to a diameter between 30 μm and 50 μm . However, the trend towards miniaturization continues and reduces the bump diameter, which increases the current density in the solder ball.
More performance and increasingly smaller form factors are the drivers for these advanced manufacturing processes in advanced packaging. The end products, whether smartphones or high-end servers, require constant improvements in computing power, higher I/O density and smaller form factors. To achieve these features, the technical requirements for the process flow are becoming more and more demanding.
The standard process flow for the fabrication of interconnections and solder bumps is as follows: Barrier layer deposition, structuring, coating, photoresist (PR) strip and etching. Increasingly, designers are using redistribution layers (RDLs) in flip chip designs to redistribute I/O pads to bump pads without changing the location of the I/O pads. Under bump metallization (UBM) is the critical interface between the metal pad of the IC (or Cu or Al path) and the solder, therefore high reliability is required.
An under bump metallisation (UBM) and redistribution layer interconnect conductor structure includes an RDL generated over a die. The RDL contains a first conductive area and a second conductive area. These two conductive sections are at the same level in the RDL and are separated from each other by insulating material. A UBM layer is formed above the RDL, which contains a conductive track and a conductive UBM pad. The conductive path electrically couples the first conductive section of the RDL with the second conductive section. The UBM pad is electrically connected to the second conductive section of the RDL. A conductive contact is formed over the UBM pad and electrically connected to the pad.
The progress towards higher I/O density with improved reliability and performance is leading to a general trend towards smaller conductor paths and space geometries with smaller bump diameters and pitch. The line/space dimensions are reduced from more than 10 µm to 2 µm, while the bump diameters will decrease to 10 µm in the future. This represents a particular challenge for the lithography steps as well as for the PR strip and RDL/UBM etching steps.
With decreasing dimensions and increasing packaging density it becomes more and more difficult to remove the photoresist from the individual feature. In the PR strip process, solvent diffuses into the resist, swells the resist, which is finally removed. With decreasing dimensions, the solvent's ability to penetrate the resist is limited, affecting the performance of the strip. Longer reaction times are required to achieve good photoresist removal, which has a negative effect on throughput.
Reducing the dimensions of lines/spaces is an equally important challenge for RDL/UBM etching processes. A key requirement for these etching steps is to minimize the undercuts and simultaneously remove the barrier layer. Higher undercut values impair the mechanical stability of the device, while insufficient ablation leads to poor component yields. With larger features, the influence of the undercut is smaller, because it only affects a small amount of the feature diameter. When features are reduced from 10 µm to 1 µm, the same undercut has an effect ten times greater. To minimize these overetching problems, better process control is needed to accurately detect when the etch step is complete, resulting in less undercut and leaving the critical dimension (CD) of the feature (line or bump) unaffected.
A variety of measurement tasks have to be solved in the process-oriented control in the production of RDL, UBM and solder bumps in advanced packaging. On materials that vary strongly in terms of structure and reflectivity, the measurement tasks include line metallization thickness, width and roughness, polymer thickness and stress, UBM height and roughness, solder bump height, width, pitch, coplanarity and defect inspection.
The analysis of BGAs and solder bumps requires a measurement method that captures the topography of these structures in a non-contact, fast and reliable way. Highly reflective metal surfaces must be measured just as reliably as reflective coating and rough substrate surfaces. The determination of the volume of solder bumps requires a system that also detects strongly sloped surfaces. In order to measure the highly structured surface of a BGA, gaps and rapid changes in the surface must also be detected free of artifacts. A machine with a high measuring speed and a high throughput is required for process-oriented and inline control.
With optical multi-sensor measuring tools from FRT, all these measuring tasks can be performed in one tool. The system is therefore able to record large measuring fields, but also offers the possibility to record small surface areas or profiles with high resolution. Thus, the individual shapes of solder bumps can be determined and roughness and waviness can be determined from profile data as well as from 3D topography measurements. The measurement is fast, non-contact and therefore non-destructive. For process-oriented control, the required individual measuring tasks can be repeatedly executed and logged in an automated measuring sequence. If necessary, the alignment of the measuring objects can be determined by means of image analysis in order to adapt the position of the previously defined measuring positions to the sample position.
As a result of the multi-sensor concept we follow, the 3D surface measuring tools of the proven MicroProf® series can be equipped with point and area sensors for topography measurement as well as with layer thickness sensors. If required, additional sensors can be integrated. If an atomic force microscope is integrated, topography measurements with sub-nm resolution can be performed with the described measuring system. In combination with a high-precision xy stage and powerful analysis software for recording and evaluating the measurement data, a measurement tool is obtained which offers the customer a maximum of flexibility and solves the mentioned measurement tasks in RDL, UBM and solder bump control.
FRT offers both manual and fully integrated measurement solutions with robotic wafer handling, recipe creation, automatic evaluation of measurement data and a SEMI-compliant SECS/GEM interface for connection to the Fab Host. Thanks to the modular multi-sensor concept, the tools can also keep pace with ambitious roadmaps in advanced packaging and optimize the yield of your production.
Whether for laboratory, development, quality assurance or production - FRT offers the right measurement technology for your application from Advanced Packaging. Do not hesitate to contact us if you have any questions. Our experts will be glad to support you in solving your measurement tasks by creating the best possible system configuration for you.
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