Halbleiter / Mikroelektronik

Semiconductors

The key words are 3D IC, TSV or FOWLP. In the semi-conductor industry innovations come thick and fast, however, new solutions have as yet not been established. This is partly true for applications driven by either IoT or automotive electronics. Using FRT multi-sensor metrology tools you can keep up with the high rate of innovations and yet remain flexible for the necessary change in trend. 

WAFER THICKNESS / TTV

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SEMI-compliant thickness and TTV measurement

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Full wafer thickness map in 3D view, polished Si wafer

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4 profiles of a polished Si wafer showing thickness variation

GLOBAL / LOCAL WAFER PARAMETERS

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Measurement of global and local wafer parameters

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Full wafer thickness map in 3D view

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Wafer map with local parameters (LTIR, LTV, LT, LFPD, etc.)

FILM THICKNESS / LAYER STACK

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Thin film and layer stack measurement

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Film thickness, SiO2 layer on a Si wafer

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Film thickness analysis of a 500 nm SiO2 layer on a Si wafer using a fit algorithm

HYBRID METROLOGY

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Combination of different sensors, automated calculation of the desired sample parameters

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Example of hybrid metrology

BUMPS

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Bump dimensions and coplanarity

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Area measurement of a bump array

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Profile measurement of a bump array

ROUGHNESS

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DIN/ISO-compliant roughness and waviness measurement

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Area measurement of a polished Si wafer, sRa = 0.766 nm

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Profile measurement of a Si wafer, Ra = 13.8 nm

BOND LAYER / THICKNESS / VOIDS

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Bond layer thickness using IR technology

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Four thickness profiles (star pattern) across a bonded wafer

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Detection of voids in the bond interface

STRUCTURE DETECTION (IR)

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Imaging of hidden structures using IR microscope

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DISCO HI-TEC EUROPE GmbH, Stealth laser grooves in a bare Si wafer

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Alignment mark on a cavity-SOI wafer

OVERLAY

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Overlay measuremenmt

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Automatic recognition of marks and determination of overlay shift

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Overlay map: example of display of overlay errors

VIAS / TSV

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High aspect ratio vias and TSV

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Area measurement of a single TSV

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Profile measurement of a single TSV (depth, top & bottom CD)

TRENCHES

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High aspect ratio trenches

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Area measurement of a wafer with trenches

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Profile measurement of a single trench

DEFECT INSPECTION / VOIDS

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Defect inspection

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3D topography of a Si wafer with voids

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3D topography of a dimple on a Si wafer

TOPOGRAPHY (SHAPE, STRUCTURE)

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Standard topography measurement

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Area measurement of a SiO2 membrane

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Profile measurement of a SiO2 membrane

BOW / WARP

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SEMI-compliant bow and warp measurement

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Full wafer map of a Si wafer in 3D view showing bow

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Profile of the top topography of a Si wafer

WAFER THICKNESS (IR)

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Wafer thickness and layer thickness using IR technology

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Thickness of a Si wafer, post grinding

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Thickness of a Si membrane

REMAINING SILICON THICKNESS (RST)

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RST measurement using IR technology

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Thickness of a bonded Si wafer, device wafer before grinding

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Thickness of a bonded Si wafer, device wafer after grinding/etching

STRESS

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Wafer stress measurement

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Wafer bow before thin film deposition

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Wafer bow after thin film deposition

NANOTOPOGRAPHY

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Nanotopography on polished and ground wafers

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Full area measurement of a 300 mm Si wafer

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Result map after filtering shows nanotopography features

SAW MARKS

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Automated detection and reporting of saw marks

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Area measurement of saw marks on a Si wafer

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Topography of a Si wafer along the blue line

ROLL-OFF AMOUNT / EDGE TRIM

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SEMI-compliant roll-off measurement

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Roll off Amount (RoA) profile pattern

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Profile on the edge of a Si wafer

THERMAL LOAD

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Optical metrology at variable sample temperature

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Warpage of a chip relative to PCB at 30°C

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Warpage of a chip relative to PCB at 120°C