Silicon goes 3D – Advanced Packaging

The wafer-level packaging processes are concerned with producing the chip on the wafer instead of first cutting it into individual chips and then processing it. Such technologies deliver greater bandwidth, speed and reliability, consume less power, and offer a wider range of designs for multi-chip applications such as mobile consumer electronics, high-end supercomputing and internet-of-things devices. WLP has enabled the industry to develop from wire bonding to flip-chip processes, 2.5D interposer and TSV technology, and most recently to 2D and 3D fan-out processes with high densities of connections in the smallest of spaces. In FOWLP, individual chips are assembled into an artificial wafer made of low-cost polymer materials with additional space for connections. An RDL redirects the connections on the chip to the edge areas. The advantages of FOWLP include improved performance per watt and a wider range of different designs due to thinner packages. Depending on the relevance of the design, cost, power consumption, performance and reliability, these different processes are used.

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Before WLP, the chips were connected to a substrate by wire bonding, with wires attached to the edges of the chip. Only as many wires could be used as would fit around the chip. The wires were also relatively long, resulting in a time delay and wasted energy. Over the years, circuits have been reduced in size and the contact wires have become smaller and smaller in diameter and have moved closer together. In order to avoid this problem, flip-chip packaging was developed as a process. This principle replaces wires with bumps (i. e. connection points or pads) on the entire surface of the wafer to increase the surface density of the electrical connections.

Area measurement of Through Silicon Vias (TSVs)
Profile measurement of a single TSV (depth, CD top & bottom)

By stacking chips and using vertical connections that pass through them, more bandwidth and less power consumption can be achieved. This TSV technology can also be used to connect chips on the same plane using a silicon interposer connected to a substrate by copper pillars. A silicon interposer has vertical TSVs and horizontal, multi-layered, dense copper interconnections. This technology, called 2.5D, can be used in servers, image sensors and other high-performance systems. When TSV-capable chips are stacked on top of each other and connected with bumps (and possibly RDL), they form 3D-integrated chips.

The established devices of the MicroProf® series, e.g. in combination with the white light interferometers WLI PL and WLI FL, offer optical and non-contact innovative solutions in the field of advanced packaging for production, research and development where other processes reach their limits. For example, plasma diced etch trenches have depths of 50 to 200 µm, which are far beyond the reach of AFM or profilometer tips. Many optical methods such as confocal microscopy are also not suitable for this measurement due to their aperture, as no light from the bottom of the trenches can get back into the sensor due to the shadowing of the side walls. In addition, the etching process leads to a roughening of the surface in the etching trenches and thus to high differences in the reflectivity between the substrate surface and the bottom of the trenches, which can lead to problems during measurement. Thanks to its parallel illumination, the WLI PL is excellently suited for the measurement of such deep trenches with a high aspect ratio, since a large proportion of the light reaches the bottom of the etching structure and the depth can thus be measured. Depending on the surface texture, structures with minimum widths from 2 to 3 µm and aspect ratios of up to 50:1 (depth to width) can be measured. The use of a special measuring mode enables the measurement in two measuring steps. The substrate surface and the bottom of the structures are measured in such a way that an optimal adaptation of the measuring parameters to the different surface conditions is achieved.

Area measurement of a wafer with trenches

Another problem for measurement technology is often the small lateral dimension of the structures, since the optical resolution of the methods is usually not high enough. Trenches, for example, can have trench widths of less than 1 µm. The WLI FL uses a special algorithm to determine the depth of etching structures down to 0.7 µm in width. In this case, the aspect ratio can be up to 3:1. This opens up dimensions that have not been reached so far. This method makes it possible to measure all currently used variants of TSVs, including vias with diameters of less than one micrometer that are no longer optically detectable. It is remarkable that the individual via is actually measured and not a statistical effect.

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